`timescale 1ns / 1ns
module VgaControllerTest  ; 
  reg   iEn   ; 
  reg   iRstN   ; 
  wire  oVgaHs   ; 
  wire  [3:0]  oVgaRgb   ; 
  wire  [9:0]  oVgaX   ; 
  wire  [18:0]  oAddress   ; 
  wire  oVgaVs   ; 
  wire  [9:0]  oVgaY   ; 
  wire  oReadEn   ; 
  reg   iClk   ; 
  reg  [3:0]  iData   ; 
  VgaController DUT  ( 
       .iEn (iEn ) ,
      .iRstN (iRstN ) ,
      .oVgaHs (oVgaHs ) ,
      .oVgaRgb (oVgaRgb ) ,
      .oVgaX (oVgaX ) ,
      .oAddress (oAddress ) ,
      .oVgaVs (oVgaVs ) ,
      .oVgaY (oVgaY ) ,
      .oReadEn (oReadEn ) ,
      .iClk (iClk ) ,
      .iData (iData ) ); 



// "Constant Pattern"
// Start Time = 0 ns, End Time = 20 ms, Period = 0 ns
  initial
  begin
	  iData  = 4'b1010  ;
	 # 20000000 ;
// dumped values till 20 ms
  end


// "Clock Pattern" : dutyCycle = 50
// Start Time = 0 ns, End Time = 20 ms, Period = 40 ns
  initial
  begin
	iClk  = 1'b0  ;
	repeat(500000) begin
	  # 20	  iClk  = 1'b1  ;
	  # 20	  iClk  = 1'b0  ;
	end
  end


// "Constant Pattern"
// Start Time = 0 ns, End Time = 20 ms, Period = 0 ns
  initial
  begin
	  iRstN  = 1'b1  ;
	  # 20000000 ;
// dumped values till 20 ms
  end


// "Constant Pattern"
// Start Time = 0 ns, End Time = 20 us, Period = 0 ns
  initial
  begin
	  iEn  = 1'b1  ;
	  # 20000000;
// dumped values till 20 ms
  end

  initial
	#20000000 $stop;
endmodule
